SPARC Processor History and Future:
The Roadmap to Throughput Computing

Abstract - This session will discuss the major trends in microprocessor technology that have resulted in the relentless progress in price/performance exhibited by these devices over the past 20 years. The SPARC processor will be used as an illustrative example, including comparisons to other current major 64-bit architectures, notably POWER and EPIC (Itanium). The case will be made that further progress along the crucial price/performance axis for all current high-end architectures is threatened by the same law of diminishing returns, manifesting itself as a visible and rising tide of inefficiency in the use both of on-chip resources and clock cycles. The solution to this problem of rapidly growing processor inefficiency being adopted at Sun for future SPARC/Solaris platforms, namely a radical shift in the direction of "throughput computing," enabled at the processor level by new "Chip MultiThreaded" or CMT processors, will be explained. The potential of CMT design to produce up to a 30X performance improvement in next-generation SPARC processors will be justified, and the CMT solution will be contrasted with alternative proposals that attempt to address the same problem, like Symmetric Multithreading (SMT).